In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, has remained substantially constant. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal. Many traditional deposition processes such as chemical vapor deposition (CVD) have difficulty filling increasingly high aspect ratio features, for example, where the aspect ratio exceeds 2:1, and particularly where it exceeds 4:1.
As a result of these process limitations, electroplating or electrodeposition, which has previously been limited to the fabrication of patterns on circuit boards, is now emerging as a preferable method for filling metal interconnects structures such as via openings (holes) and trench line openings on semiconductor devices. Typically, electroplating uses a suspension of positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate, as a source of electrons, to deposit (plate out) the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first deposited on the semiconductor wafer and in etched features to provide an electrical path across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface is electroplated with an appropriate metal, for example, aluminum or copper.
One exemplary process for forming a series of interconnected multiple layers, for example, is a dual damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a dual damascene process, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects to electrically interconnect areas within the multilayer device and contact layers to interconnect the various devices on the chip surface. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multilayer device. Metal interconnect lines (trench lines) typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Vias and trench lines (metal interconnects) are selectively interconnected in order to form the necessary electrical connections. In forming a dual damascene structure, via openings (holes) and trench line openings are anisotropically etched into the insulating layers and are back-filled with metal. The insulating layers where metal interconnect lines (trench lines) are formed are typically referred to as metallization layers and the insulating layer including interconnecting vias are referred to as inter-metal dielectric (IMD) layers. The IMD layers preferably include a low-k (low dielectric constant) insulating material which reduces signal delay times caused by parasitic capacitance. The process by which via openings (holes) and trench lines are selectively etched into the insulating layers is typically a photolithographic masking process, followed by a reactive ion etch (RIE) process, both of which are commonly known in the art.
In filling the via openings and trench line openings with metal, for example, copper, electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes first depositing a barrier layer over the etched opening surfaces, such as via openings and trench line openings, depositing a metal seed layer, preferably copper, over the barrier layer, and then electroplating a metal, again preferably copper, over the seed layer to fill the etched features to form, for example, vias and trench lines. Finally, the deposited layers and the dielectric layers are planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Metal electroplating in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution including an anode with the electrolyte impinging perpendicularly on the plating surface. The plating surface is contacted with an electrical power source forming the cathode of the plating system such that ions in the plating solution deposit on the conductive portion of the plating surface.
One method for providing power to the plating surface uses, for example cathode contacts (e.g., pins, ‘fingers’, or springs) which contact the plating surface at a cathode contact area which may include a seed layer of metal. The cathode contacts make contact with the cathode contact area which includes a metal layer formed as close as possible to the edge (periphery) of the semiconductor wafer to minimize the wasted area on the wafer due to the cathode contact areas. In order to minimize resistance between the cathode contacts and the cathode contact areas, force is applied to the cathode contacts to assure intimate contact with the seed layer in the cathode contact areas. A shortcoming in the prior art is that, frequently, the electroplating process results in the delamination or peeling of the uppermost insulating (IMD) layers, especially underlying the cathode contact areas, due to the stress induced by the force applied by the cathode contact pins to the metal layer or cathode contact pad. The metal layer or cathode contact pads in the cathode contact areas at the edge of the wafer are typically formed over an uppermost insulating (IMD) layer devoid of etched semiconductor features such as vias and trench lines. However, co-pending application Ser. No. 10/316,677, which is incorporated herein by reference in its entirety, provides a method for strengthening the underlying insulating layer to resist delamination or cracking caused by the cathode contact pins by forming metal interconnects in the insulating layer in the cathode contact area.
The delamination and cracking problem is, however, exacerbated by the use of low-k (low dielectric) material in insulating (IMD) layers, for example, carbon doped silicon dioxide. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials have become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. One consequence of using porous low-k materials in insulating layers is that the insulating layers have reduced strength and are prone to delamination (peeling) and cracking when they are subjected to processing stresses, for example, stresses induced by the forces applied by electroplating cathode contacts.
FIG. 1A, shows for example, a side view of a cathode contact pin 10 according to the prior art for making contact with the metal seed layer or cathode contact pad in a cathode contact area. According to the prior art, the tip region 12 of the cathode contact pin 10 typically has an angled surface forming an angle theta 14 at the pointed tip 16, designed to slightly penetrate the cathode contact pad to provide a low resistance contact. For example, as shown in a top view of the tip region 12 in FIG. 1B, the tip region 12 of the cathode contact pin 10 may include faceted surfaces 18 that form a pyramidal shape that, for example, includes four angled surfaces forming pointed tip 16 for slightly penetrating a metal surface. A shortcoming of the pointed tip cathode contact pin according to the prior art is that the force applied by the cathode contact pin is distributed over a small area of the cathode contact surface resulting in a force per unit area that is incompatible with current semiconductor processing technologies.
As such, metal seed layers or cathode contact pads including relatively ductile copper or copper alloy, are easily penetrated and disturbed, causing the applied forces to be further concentrated on the underlying insulating layer. Consequently, newer low-k materials used for the insulating layers, which are frequently porous, are not able to withstand applied forces typically applied with a pointed tip design cathode contact pin. As a result, delamination and cracking of the insulating layer may accompany the electroplating process or occur is subsequent semiconductor wafer processing steps resulting in lower semiconductor wafer yields. Further, as the trend in semiconductor device manufacturing is to increase the number of layers in a multilayer device structure, the problem is further exacerbated by the additive buildup of stresses as more layers are included in multilayer structures.
There is therefore a need in the semiconductor processing art to develop an improved electroplating cathode contact pin that is compatible with current semiconductor manufacturing technologies whereby forces are better distributed to avoiding delamination or cracking of the insulating layers while achieving low resistance electrical contact with cathode contact areas.
It is therefore an object of the invention to provide an improved electroplating cathode contact pin that is compatible with current semiconductor manufacturing technologies whereby forces applied by the cathode contact pin are better distributed thereby avoiding delamination or cracking of the insulating layers while achieving low resistance electrical contact with cathode contact areas in addition to overcoming other shortcomings and deficiencies in the prior art.